#ifndef __NUC_CLK_H__
#define __NUC_CLK_H__

#include "nuc970.h"

#define REG_BITS_SET(reg, pos, msk, val) outpw(reg,(inpw(reg)&(~(((uint32_t)(msk))<<(pos))))|((((uint32_t)(val))<<(pos)))))
#define REG_BITS_GET(reg, pos, num) ((inpw(reg) >> (pos)) & (~(((0xFFFFFFFFUL >> (32 - num))))))
#define REG_BIT_SET(reg, pos) outpw(reg, inpw(reg) | (1UL << (pos)))
#define REG_BIT_CLR(reg, pos) outpw(reg, inpw(reg) & (~(1UL << (pos))))
#define REG_BIT_GET(reg, pos) ((inpw(reg) >> (pos)) & 0x01UL)

//CLK_DIVCTL4
#define CLK_UART3_N(x)      REG_BITS_SET(REG_CLK_DIVCTL4, 29, 0x07UL, (x - 1)) //x=1..8
#define CLK_UART3_S_XIN()   outpw(REG_CLK_DIVCTL4, (inpw(REG_CLK_DIVCTL4) & (~(3UL << 27))) | (0UL << 27))
#define CLK_UART3_S_ACLK()  outpw(REG_CLK_DIVCTL4, (inpw(REG_CLK_DIVCTL4) & (~(3UL << 27))) | (2UL << 27))
#define CLK_UART3_S_UCLK()  outpw(REG_CLK_DIVCTL4, (inpw(REG_CLK_DIVCTL4) & (~(3UL << 27))) | (3UL << 27))
#define CLK_UART3_SDIV(x)   outpw(REG_CLK_DIVCTL4, (inpw(REG_CLK_DIVCTL4) & (~(7UL << 24))) | (((uint32_t)(x - 1)) << 24)) //x=1..8

#define CLK_UART2_N(x)      REG_BITS_SET(REG_CLK_DIVCTL4, 21, 0x07UL, (x - 1)) //x=1..8
#define CLK_UART2_S_XIN()   outpw(REG_CLK_DIVCTL4, (inpw(REG_CLK_DIVCTL4) & (~(3UL << 19))) | (0UL << 19))
#define CLK_UART2_S_ACLK()  outpw(REG_CLK_DIVCTL4, (inpw(REG_CLK_DIVCTL4) & (~(3UL << 19))) | (2UL << 19))
#define CLK_UART2_S_UCLK()  outpw(REG_CLK_DIVCTL4, (inpw(REG_CLK_DIVCTL4) & (~(3UL << 19))) | (3UL << 19))
#define CLK_UART2_SDIV(x)   outpw(REG_CLK_DIVCTL4, (inpw(REG_CLK_DIVCTL4) & (~(7UL << 16))) | (((uint32_t)(x - 1)) << 16)) //x=1..8

#define CLK_UART1_N(x)      REG_BITS_SET(REG_CLK_DIVCTL4, 13, 0x07UL, (x - 1)) //x=1..8
#define CLK_UART1_S_XIN()   outpw(REG_CLK_DIVCTL4, (inpw(REG_CLK_DIVCTL4) & (~(3UL << 11))) | (0UL << 11))
#define CLK_UART1_S_ACLK()  outpw(REG_CLK_DIVCTL4, (inpw(REG_CLK_DIVCTL4) & (~(3UL << 11))) | (2UL << 11))
#define CLK_UART1_S_UCLK()  outpw(REG_CLK_DIVCTL4, (inpw(REG_CLK_DIVCTL4) & (~(3UL << 11))) | (3UL << 11))
#define CLK_UART1_SDIV(x)   outpw(REG_CLK_DIVCTL4, (inpw(REG_CLK_DIVCTL4) & (~(7UL << 8))) | (((uint32_t)(x - 1)) << 8)) //x=1..8

#define CLK_UART0_N(x)      REG_BITS_SET(REG_CLK_DIVCTL4, 5, 0x07UL, (x - 1)) //x=1..8
#define CLK_UART0_S_XIN()   outpw(REG_CLK_DIVCTL4, (inpw(REG_CLK_DIVCTL4) & (~(3UL << 3))) | (0UL << 3))
#define CLK_UART0_S_ACLK()  outpw(REG_CLK_DIVCTL4, (inpw(REG_CLK_DIVCTL4) & (~(3UL << 3))) | (2UL << 3))
#define CLK_UART0_S_UCLK()  outpw(REG_CLK_DIVCTL4, (inpw(REG_CLK_DIVCTL4) & (~(3UL << 3))) | (3UL << 3))
#define CLK_UART0_SDIV(x)   outpw(REG_CLK_DIVCTL4, (inpw(REG_CLK_DIVCTL4) & (~(7UL << 0))) | (((uint32_t)(x - 1)) << 0)) //x=1..8

//CLK_DIVCTL5
#define CLK_UART7_N(x)      REG_BITS_SET(REG_CLK_DIVCTL5, 29, 0x07UL, (x - 1)) //x=1..8
#define CLK_UART7_S_XIN()   outpw(REG_CLK_DIVCTL5, (inpw(REG_CLK_DIVCTL5) & (~(3UL << 27))) | (0UL << 27))
#define CLK_UART7_S_ACLK()  outpw(REG_CLK_DIVCTL5, (inpw(REG_CLK_DIVCTL5) & (~(3UL << 27))) | (2UL << 27))
#define CLK_UART7_S_UCLK()  outpw(REG_CLK_DIVCTL5, (inpw(REG_CLK_DIVCTL5) & (~(3UL << 27))) | (3UL << 27))
#define CLK_UART7_SDIV(x)   outpw(REG_CLK_DIVCTL5, (inpw(REG_CLK_DIVCTL5) & (~(7UL << 24))) | (((uint32_t)(x - 1)) << 24)) //x=1..8

#define CLK_UART6_N(x)      REG_BITS_SET(REG_CLK_DIVCTL5, 21, 0x07UL, (x - 1)) //x=1..8
#define CLK_UART6_S_XIN()   outpw(REG_CLK_DIVCTL5, (inpw(REG_CLK_DIVCTL5) & (~(3UL << 19))) | (0UL << 19))
#define CLK_UART6_S_ACLK()  outpw(REG_CLK_DIVCTL5, (inpw(REG_CLK_DIVCTL5) & (~(3UL << 19))) | (2UL << 19))
#define CLK_UART6_S_UCLK()  outpw(REG_CLK_DIVCTL5, (inpw(REG_CLK_DIVCTL5) & (~(3UL << 19))) | (3UL << 19))
#define CLK_UART6_SDIV(x)   outpw(REG_CLK_DIVCTL5, (inpw(REG_CLK_DIVCTL5) & (~(7UL << 16))) | (((uint32_t)(x - 1)) << 16)) //x=1..8

#define CLK_UART5_N(x)      REG_BITS_SET(REG_CLK_DIVCTL5, 13, 0x07UL, (x - 1)) //x=1..8
#define CLK_UART5_S_XIN()   outpw(REG_CLK_DIVCTL5, (inpw(REG_CLK_DIVCTL5) & (~(3UL << 11))) | (0UL << 11))
#define CLK_UART5_S_ACLK()  outpw(REG_CLK_DIVCTL5, (inpw(REG_CLK_DIVCTL5) & (~(3UL << 11))) | (2UL << 11))
#define CLK_UART5_S_UCLK()  outpw(REG_CLK_DIVCTL5, (inpw(REG_CLK_DIVCTL5) & (~(3UL << 11))) | (3UL << 11))
#define CLK_UART5_SDIV(x)   outpw(REG_CLK_DIVCTL5, (inpw(REG_CLK_DIVCTL5) & (~(7UL << 8))) | (((uint32_t)(x - 1)) << 8)) //x=1..8

#define CLK_UART4_N(x)      REG_BITS_SET(REG_CLK_DIVCTL5, 5, 0x07UL, (x - 1)) //x=1..8
#define CLK_UART4_S_XIN()   outpw(REG_CLK_DIVCTL5, (inpw(REG_CLK_DIVCTL5) & (~(3UL << 3))) | (0UL << 3))
#define CLK_UART4_S_ACLK()  outpw(REG_CLK_DIVCTL5, (inpw(REG_CLK_DIVCTL5) & (~(3UL << 3))) | (2UL << 3))
#define CLK_UART4_S_UCLK()  outpw(REG_CLK_DIVCTL5, (inpw(REG_CLK_DIVCTL5) & (~(3UL << 3))) | (3UL << 3))
#define CLK_UART4_SDIV(x)   outpw(REG_CLK_DIVCTL5, (inpw(REG_CLK_DIVCTL5) & (~(7UL << 0))) | (((uint32_t)(x - 1)) << 0)) //x=1..8

//CLK_DIVCTL6
#define CLK_SMC1_N(x)       outpw(REG_CLK_DIVCTL6, (inpw(REG_CLK_DIVCTL6) & (~(15UL << 28))) | (((uint32_t)(x - 1)) << 28)) //x=1..16
#define CLK_SMC0_N(x)       outpw(REG_CLK_DIVCTL6, (inpw(REG_CLK_DIVCTL6) & (~(15UL << 24))) | (((uint32_t)(x - 1)) << 24)) //x=1..16

#define CLK_UART10_N(x)     outpw(REG_CLK_DIVCTL6, (inpw(REG_CLK_DIVCTL6) & (~(7UL << 21))) | (((uint32_t)(x - 1)) << 21)) //x=1..8
#define CLK_UART10_S_XIN()  outpw(REG_CLK_DIVCTL6, (inpw(REG_CLK_DIVCTL6) & (~(3UL << 19))) | (0UL << 19))
#define CLK_UART10_S_ACLK() outpw(REG_CLK_DIVCTL6, (inpw(REG_CLK_DIVCTL6) & (~(3UL << 19))) | (2UL << 19))
#define CLK_UART10_S_UCLK() outpw(REG_CLK_DIVCTL6, (inpw(REG_CLK_DIVCTL6) & (~(3UL << 19))) | (3UL << 19))
#define CLK_UART10_SDIV(x)  outpw(REG_CLK_DIVCTL6, (inpw(REG_CLK_DIVCTL6) & (~(7UL << 16))) | (((uint32_t)(x - 1)) << 16)) //x=1..8

#define CLK_UART9_N(x)      outpw(REG_CLK_DIVCTL6, (inpw(REG_CLK_DIVCTL6) & (~(7UL << 13))) | (((uint32_t)(x - 1)) << 13)) //x=1..8
#define CLK_UART9_S_XIN()   outpw(REG_CLK_DIVCTL6, (inpw(REG_CLK_DIVCTL6) & (~(3UL << 11))) | (0UL << 11))
#define CLK_UART9_S_ACLK()  outpw(REG_CLK_DIVCTL6, (inpw(REG_CLK_DIVCTL6) & (~(3UL << 11))) | (2UL << 11))
#define CLK_UART9_S_UCLK()  outpw(REG_CLK_DIVCTL6, (inpw(REG_CLK_DIVCTL6) & (~(3UL << 11))) | (3UL << 11))
#define CLK_UART9_SDIV(x)   outpw(REG_CLK_DIVCTL6, (inpw(REG_CLK_DIVCTL6) & (~(7UL << 8))) | (((uint32_t)(x - 1)) << 8)) //x=1..8

#define CLK_UART8_N(x)      outpw(REG_CLK_DIVCTL6, (inpw(REG_CLK_DIVCTL6) & (~(7UL << 5))) | (((uint32_t)(x - 1)) << 5)) //x=1..8
#define CLK_UART8_S_XIN()   outpw(REG_CLK_DIVCTL6, (inpw(REG_CLK_DIVCTL6) & (~(3UL << 3))) | (0UL << 3))
#define CLK_UART8_S_ACLK()  outpw(REG_CLK_DIVCTL6, (inpw(REG_CLK_DIVCTL6) & (~(3UL << 3))) | (2UL << 3))
#define CLK_UART8_S_UCLK()  outpw(REG_CLK_DIVCTL6, (inpw(REG_CLK_DIVCTL6) & (~(3UL << 3))) | (3UL << 3))
#define CLK_UART8_SDIV(x)   outpw(REG_CLK_DIVCTL6, (inpw(REG_CLK_DIVCTL6) & (~(7UL << 0))) | (((uint32_t)(x - 1)) << 0)) //x=1..8

//CLK_DIVCTL7
#define CLK_ADC_N(x)        outpw(REG_CLK_DIVCTL7, (inpw(REG_CLK_DIVCTL7) & (~(255UL << 24))) | (((uint32_t)(x - 1)) << 24)) //x=1..256
#define CLK_ADC_S_XIN()     outpw(REG_CLK_DIVCTL7, (inpw(REG_CLK_DIVCTL7) & (~(3UL << 19))) | (0UL << 19))
#define CLK_ADC_S_ACLK()    outpw(REG_CLK_DIVCTL7, (inpw(REG_CLK_DIVCTL7) & (~(3UL << 19))) | (2UL << 19))
#define CLK_ADC_S_UCLK()    outpw(REG_CLK_DIVCTL7, (inpw(REG_CLK_DIVCTL7) & (~(3UL << 19))) | (3UL << 19))
#define CLK_ADC_SDIV(x)     outpw(REG_CLK_DIVCTL7, (inpw(REG_CLK_DIVCTL7) & (~(7UL << 16))) | (((uint32_t)(x - 1)) << 16)) //x=1..8

#define CLK_GPIO_S_XIN()    outpw(REG_CLK_DIVCTL7, (inpw(REG_CLK_DIVCTL7) & (~(1UL << 7))))
#define CLK_GPIO_S_X32()    outpw(REG_CLK_DIVCTL7, (inpw(REG_CLK_DIVCTL7) | ((1UL << 7))))
#define CLK_GPIO_N(x)       outpw(REG_CLK_DIVCTL7, (inpw(REG_CLK_DIVCTL7) & (~(127UL << 0))) | (((uint32_t)(x - 1)) << 0)) //x=1..128

//CLK_DIVCTL8
#define CLK_S_ETIMER3_POS 28
#define CLK_S_ETIMER2_POS 24
#define CLK_S_ETIMER1_POS 20
#define CLK_S_ETIMER0_POS 16
#define CLK_S_WWDT_POS 12
#define CLK_S_WDT_POS 8
#define CLK_S_MII_POS 0
#define CLK8_SEL(pos, val) outpw(REG_CLK_DIVCTL8, (inpw(REG_CLK_DIVCTL8) & (~(3UL << pos))) | ((uint32_t)(val) << pos))

#define CLK_ETIMER0_S_XIN()             CLK8_SEL(CLK_S_ETIMER0_POS, 0UL)
#define CLK_ETIMER0_S_PCLK()            CLK8_SEL(CLK_S_ETIMER0_POS, 1UL)
#define CLK_ETIMER0_S_PCKL_DIV4096()    CLK8_SEL(CLK_S_ETIMER0_POS, 2UL)
#define CLK_ETIMER0_S_X32()             CLK8_SEL(CLK_S_ETIMER0_POS, 3UL)
#define CLK_ETIMER1_S_XIN()             CLK8_SEL(CLK_S_ETIMER1_POS, 0UL)
#define CLK_ETIMER1_S_PCLK()            CLK8_SEL(CLK_S_ETIMER1_POS, 1UL)
#define CLK_ETIMER1_S_PCKL_DIV4096()    CLK8_SEL(CLK_S_ETIMER1_POS, 2UL)
#define CLK_ETIMER1_S_X32()             CLK8_SEL(CLK_S_ETIMER1_POS, 3UL)
#define CLK_ETIMER2_S_XIN()             CLK8_SEL(CLK_S_ETIMER2_POS, 0UL)
#define CLK_ETIMER2_S_PCLK()            CLK8_SEL(CLK_S_ETIMER2_POS, 1UL)
#define CLK_ETIMER2_S_PCKL_DIV4096()    CLK8_SEL(CLK_S_ETIMER2_POS, 2UL)
#define CLK_ETIMER2_S_X32()             CLK8_SEL(CLK_S_ETIMER2_POS, 3UL)
#define CLK_ETIMER3_S_XIN()             CLK8_SEL(CLK_S_ETIMER3_POS, 0UL)
#define CLK_ETIMER3_S_PCLK()            CLK8_SEL(CLK_S_ETIMER3_POS, 1UL)
#define CLK_ETIMER3_S_PCKL_DIV4096()    CLK8_SEL(CLK_S_ETIMER3_POS, 2UL)
#define CLK_ETIMER3_S_X32()             CLK8_SEL(CLK_S_ETIMER3_POS, 3UL)
#define CLK_WWDT_S_XIN()                CLK8_SEL(CLK_S_WWDT_POS, 0UL)
#define CLK_WWDT_S_XIN_DIV128()         CLK8_SEL(CLK_S_WWDT_POS, 1UL)
#define CLK_WWDT_S_PCKL_DIV4096()       CLK8_SEL(CLK_S_WWDT_POS, 2UL)
#define CLK_WWDT_S_X32()                CLK8_SEL(CLK_S_WWDT_POS, 3UL)
#define CLK_WDT_S_XIN()                 CLK8_SEL(CLK_S_WDT_POS, 0UL)
#define CLK_WDT_S_XIN_DIV128()          CLK8_SEL(CLK_S_WDT_POS, 1UL)
#define CLK_WDT_S_PCKL_DIV4096()        CLK8_SEL(CLK_S_WDT_POS, 2UL)
#define CLK_WDT_S_X32()                 CLK8_SEL(CLK_S_WDT_POS, 3UL)

/*-------------------------reset------------------------*/
#define RST_SYMBOL_MAKE(site, pos) ((site << 8) | pos)
#define RST_AHB_CHIP        RST_SYMBOL_MAKE(0, 0)
#define RST_AHB_CPU_PLS     RST_SYMBOL_MAKE(0, 2)
#define RST_AHB_GDMA        RST_SYMBOL_MAKE(0, 3)
#define RST_AHB_I2S         RST_SYMBOL_MAKE(0, 8)
#define RST_AHB_LCD         RST_SYMBOL_MAKE(0, 9)
#define RST_AHB_CAP         RST_SYMBOL_MAKE(0, 10)
#define RST_AHB_EMAC0       RST_SYMBOL_MAKE(0, 16)
#define RST_AHB_EMAC1       RST_SYMBOL_MAKE(0, 17)
#define RST_AHB_USBH        RST_SYMBOL_MAKE(0, 18)
#define RST_AHB_USBD        RST_SYMBOL_MAKE(0, 19)
#define RST_AHB_FMI         RST_SYMBOL_MAKE(0, 20)
#define RST_AHB_GE2D        RST_SYMBOL_MAKE(0, 21)
#define RST_AHB_JPEG        RST_SYMBOL_MAKE(0, 22)
#define RST_AHB_CRYPTO      RST_SYMBOL_MAKE(0, 23)
#define RST_AHB_SDIO        RST_SYMBOL_MAKE(0, 24)

#define RST_APB0_GPIO       RST_SYMBOL_MAKE(1, 3)
#define RST_APB0_ETIMER0    RST_SYMBOL_MAKE(1, 4)
#define RST_APB0_ETIMER1    RST_SYMBOL_MAKE(1, 5)
#define RST_APB0_ETIMER2    RST_SYMBOL_MAKE(1, 6)
#define RST_APB0_ETIMER3    RST_SYMBOL_MAKE(1, 7)
#define RST_APB0_TIMER0     RST_SYMBOL_MAKE(1, 8)
#define RST_APB0_TIMER1     RST_SYMBOL_MAKE(1, 9)
#define RST_APB0_TIMER2     RST_SYMBOL_MAKE(1, 10)
#define RST_APB0_TIMER3     RST_SYMBOL_MAKE(1, 11)
#define RST_APB0_TIMER4     RST_SYMBOL_MAKE(1, 12)
#define RST_APB0_UART0      RST_SYMBOL_MAKE(1, 16)
#define RST_APB0_UART1      RST_SYMBOL_MAKE(1, 17)
#define RST_APB0_UART2      RST_SYMBOL_MAKE(1, 18)
#define RST_APB0_UART3      RST_SYMBOL_MAKE(1, 19)
#define RST_APB0_UART4      RST_SYMBOL_MAKE(1, 20)
#define RST_APB0_UART5      RST_SYMBOL_MAKE(1, 21)
#define RST_APB0_UART6      RST_SYMBOL_MAKE(1, 22)
#define RST_APB0_UART7      RST_SYMBOL_MAKE(1, 23)
#define RST_APB0_UART8      RST_SYMBOL_MAKE(1, 24)
#define RST_APB0_UART9      RST_SYMBOL_MAKE(1, 25)
#define RST_APB0_UART10     RST_SYMBOL_MAKE(1, 26)

#define RST_APB1_I2C0       RST_SYMBOL_MAKE(2, 0)
#define RST_APB1_I2C1       RST_SYMBOL_MAKE(2, 1)
#define RST_APB1_SPI0       RST_SYMBOL_MAKE(2, 4)
#define RST_APB1_SPI1       RST_SYMBOL_MAKE(2, 5)
#define RST_APB1_CNA0       RST_SYMBOL_MAKE(2, 8)
#define RST_APB1_CNA1       RST_SYMBOL_MAKE(2, 9)
#define RST_APB1_SMC0       RST_SYMBOL_MAKE(2, 12)
#define RST_APB1_SMC1       RST_SYMBOL_MAKE(2, 13)
#define RST_APB1_ADC        RST_SYMBOL_MAKE(2, 24)
#define RST_APB1_MTPC       RST_SYMBOL_MAKE(2, 26)
#define RST_APB1_PWM        RST_SYMBOL_MAKE(2, 27)

#define ph_reset_en(rst) REG_BIT_SET((REG_SYS_AHBIPRST + (4 * ((rst >> 8) & 0x03))), (rst & 0x1F))
#define ph_reset_dis(rst) REG_BIT_CLR((REG_SYS_AHBIPRST + (4 * ((rst >> 8) & 0x03))), (rst & 0x1F))

/*-------------------------------------CLK ENABLE OR DISABLE------------------------------------*/
#define CLK_SYMBOL_MAKE(site, pos) ((site << 8) | pos)
#define CLK_HCLK_CPU            CLK_SYMBOL_MAKE(0, 0)
#define CLK_HCLK_HCLK           CLK_SYMBOL_MAKE(0, 1)
#define CLK_HCLK_HCLK1          CLK_SYMBOL_MAKE(0, 2)
#define CLK_HCLK_HCLK3          CLK_SYMBOL_MAKE(0, 3)
#define CLK_HCLK_HCLK4          CLK_SYMBOL_MAKE(0,4)
#define CLK_HCLK_PCLK           CLK_SYMBOL_MAKE(0, 5)
#define CLK_HCLK_TIC            CLK_SYMBOL_MAKE(0, 7)
#define CLK_HCLK_SRAM           CLK_SYMBOL_MAKE(0, 8)
#define CLK_HCLK_EBI            CLK_SYMBOL_MAKE(0, 9)
#define CLK_HCLK_DDR            CLK_SYMBOL_MAKE(0, 10)
#define CLK_HCLK_GDMA           CLK_SYMBOL_MAKE(0, 12)
#define CLK_HCLK_CKO            CLK_SYMBOL_MAKE(0, 15)
#define CLK_HCLK_EMAC0          CLK_SYMBOL_MAKE(0, 16)
#define CLK_HCLK_EMAC1          CLK_SYMBOL_MAKE(0, 17)
#define CLK_HCLK_USBH           CLK_SYMBOL_MAKE(0, 18)
#define CLK_HCLK_USBD           CLK_SYMBOL_MAKE(0, 19)
#define CLK_HCLK_FMI            CLK_SYMBOL_MAKE(0, 20)
#define CLK_HCLK_NAND           CLK_SYMBOL_MAKE(0, 21)
#define CLK_HCLK_eMMC           CLK_SYMBOL_MAKE(0, 22)
#define CLK_HCLK_CRYPTO         CLK_SYMBOL_MAKE(0, 23)
#define CLK_HCLK_I2S            CLK_SYMBOL_MAKE(0, 24)
#define CLK_HCLK_LCD            CLK_SYMBOL_MAKE(0, 25)
#define CLK_HCLK_CAP            CLK_SYMBOL_MAKE(0, 26)
#define CLK_HCLK_SNESOR         CLK_SYMBOL_MAKE(0, 27)
#define CLK_HCLK_GE2D           CLK_SYMBOL_MAKE(0, 28)
#define CLK_HCLK_JPEG           CLK_SYMBOL_MAKE(0, 29)
#define CLK_HCLK_SDH            CLK_SYMBOL_MAKE(0, 30)

#define CLK_PCLK0_WDT           CLK_SYMBOL_MAKE(2, 0)
#define CLK_PCLK0_WWDT          CLK_SYMBOL_MAKE(2, 1)
#define CLK_PCLK0_RTC           CLK_SYMBOL_MAKE(2, 2)
#define CLK_PCLK0_GPIO          CLK_SYMBOL_MAKE(2, 3)
#define CLK_PCLK0_ETIMER0       CLK_SYMBOL_MAKE(2, 4)
#define CLK_PCLK0_ETIMER1       CLK_SYMBOL_MAKE(2, 5)
#define CLK_PCLK0_ETIMER2       CLK_SYMBOL_MAKE(2, 6)
#define CLK_PCLK0_ETIMER3       CLK_SYMBOL_MAKE(2, 7)
#define CLK_PCLK0_TIMER0        CLK_SYMBOL_MAKE(2, 8)
#define CLK_PCLK0_TIMER1        CLK_SYMBOL_MAKE(2, 9)
#define CLK_PCLK0_TIMER2        CLK_SYMBOL_MAKE(2, 10)
#define CLK_PCLK0_TIMER3        CLK_SYMBOL_MAKE(2, 11)
#define CLK_PCLK0_TIMER4        CLK_SYMBOL_MAKE(2, 12)
#define CLK_PCLK0_UART0         CLK_SYMBOL_MAKE(2, 16)
#define CLK_PCLK0_UART1         CLK_SYMBOL_MAKE(2, 17)
#define CLK_PCLK0_UART2         CLK_SYMBOL_MAKE(2, 18)
#define CLK_PCLK0_UART3         CLK_SYMBOL_MAKE(2, 19)
#define CLK_PCLK0_UART4         CLK_SYMBOL_MAKE(2, 20)
#define CLK_PCLK0_UART5         CLK_SYMBOL_MAKE(2, 21)
#define CLK_PCLK0_UART6         CLK_SYMBOL_MAKE(2, 22)
#define CLK_PCLK0_UART7         CLK_SYMBOL_MAKE(2, 23)
#define CLK_PCLK0_UART8         CLK_SYMBOL_MAKE(2, 24)
#define CLK_PCLK0_UART9         CLK_SYMBOL_MAKE(2, 25)
#define CLK_PCLK0_UART10        CLK_SYMBOL_MAKE(2, 26)

#define CLK_PCLK1_I2C0          CLK_SYMBOL_MAKE(3, 0)
#define CLK_PCLK1_I2C1          CLK_SYMBOL_MAKE(3, 1)
#define CLK_PCLK1_SPI0          CLK_SYMBOL_MAKE(3, 4)
#define CLK_PCLK1_SPI1          CLK_SYMBOL_MAKE(3, 5)
#define CLK_PCLK1_CAN0          CLK_SYMBOL_MAKE(3, 8)
#define CLK_PCLK1_CAN1          CLK_SYMBOL_MAKE(3, 9)
#define CLK_PCLK1_SMC0          CLK_SYMBOL_MAKE(3, 12)
#define CLK_PCLK1_SMC1          CLK_SYMBOL_MAKE(3, 13)
#define CLK_PCLK1_ADC           CLK_SYMBOL_MAKE(3, 24)
#define CLK_PCLK1_MTPC          CLK_SYMBOL_MAKE(3, 26)
#define CLK_PCLK1_PWM           CLK_SYMBOL_MAKE(3, 27)

#define ph_clk_en(phx)  REG_BIT_SET((REG_CLK_HCLKEN + (4 * ((phx >> 8) & 0x03))), (phx & 0x1F))
#define ph_clk_dis(phx) REG_BIT_CLR((REG_CLK_HCLKEN + (4 * ((phx >> 8) & 0x03))), (phx & 0x1F))


#endif
